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tc554161aft-70v,-85v,-10v 2001-08-17 1/11 toshiba mos digital integrated circuit silicon gate cmos 262,144-word by 16-bit static ram description the tc554161aft is a 4,194,304-bit static random access memory (sram) organized as 262,144 words by 16bits. fabricated using toshiba's cmos silicon gate process technology, this device operates from a single 2.7 to 5.5v power supply. advanced circuit technology provides both high speed and low power at an operating current of 10 ma/mhz (typ) and a minimum cycle time of 70 ns. it is automatically placed in low-power mode at 2 a standby current (typ) when chip enable ( ce ) is asserted high. there are two control inputs. ce is used to select the device and for data retention control, and output enable ( oe ) provides fast memory access. data byte control pin ( lb , ub ) provides lower and upper byte access. this device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. the tc554161aft is available in a plastic 54-pin thin -small -outline package (tsop). features low-power dissipation operating: 55mw/mhz (typical) standby current of 5 a (maximum) at ta 25c single power supply voltage of 2.7 to 5.5 v power down features using ce data retention supply voltage of 2 to 5.5 v direct ttl compatibility for all inputs and outputs pin assignment (top view) pin names a0~a17 address inputs i/o1~i/o16 data inputs/outputs ce chip enable r/w read/write control oe output enable lb , ub data byte control v dd power gnd ground nc no connection op * option * : op pin must be open of connected to gnd. access times (maximum): 5 v 10% 2.7 v~5.5 v -70v -85v -10v -70v/-85v/-10v access time 70 ns 85 ns 100 ns 150 ns ce access time 70 ns 85 ns 100 ns 150 ns oe access time 35 ns 45 ns 50 ns 75 ns package: tsop ii54-p-400-0.80 (aft) (weight:0.57g typ) nc a3 a2 a1 a0 i/o16 i/o15 v dd gnd i/o14 i/o13 op r/w i/o12 i/o11 gnd v dd i/o10 i/o9 nc a17 a16 a15 a14 a13 a 4 a 5 a 6 a 7 nc i/o1 i/o2 v dd gnd i/o3 i/o4 op nc i/o5 i/o6 gnd v dd i/o7 i/o8 a 8 a 9 a 10 a 11 a 12 nc 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 ce oe ub lb (normal pinout)
tc554161aft-70v,-85v,-10v 2001-08-17 2/11 block diagram maximum ratings symbol rating value unit v dd power supply voltage 0.3~7.0 v v in input voltage 0.3 * ~7.0 v v i/o input/output voltage 0.5~v dd 0.5 v p d power dissipation 0.6 w t solder soldering temperature (10s) 260 c t stg storage temperature 55~150 c t opr operating temperature 0~70 c * : 3.0v when measured at a pulse width of 30ns i/o1 ce v dd gnd i/o8 ce clock generator ce i/o9 i/o16 oe lb ce a5 a6 a7 a8 a9 a10 data output buffer data output buffer data input buffer data input buffer a4 a2 a3 a11 a12 a13 a14 a15 a16 a17 a1 ub r/w memory cell array 2,048 128 16 (4,194,304) column address decoder sense amp column adderss register column address buffer row address decoder row address buffer row address register a0 i/o2 i/o4 i/o5 i/o3 i/o6 i/o7 i/o13 i/o10 i/o11 i/o12 i/o15 i/o14
tc554161aft-70v,-85v,-10v 2001-08-17 3/11 dc recommended operating conditions (ta 0 to 70c) 5 v 10% 2.7 v~5.5 v symbol parameter min typ max min typ max unit v dd power supply voltage 4.5 5.0 5.5 2.7 5.0 5.5 v v ih input high voltage 2.2 v dd 0.3 v dd 0.2 v dd 0.3 v v il input low voltage 0.3 * 0.8 0.3 * 0.2 v v dh data retention supply voltage 2.0 5.5 2.0 5.5 v * : 3.0v when measured at a pulse width of 30 ns dc characteristics (ta 0 to 70c, v dd 5 v 10%) symbol parameter test condition min typ max unit i il input leakage current v in 0 v~v dd 1.0 a i lo output leakage current ce v ih or r/w v il or oe v ih , v out 0 v~v dd 1.0 a i oh output high current v oh 2.4 v 1.0 ma i ol output low current v ol 0.4 v 2.1 ma t cycle 70 ns 110 t cycle 85 ns, 100 ns 100 i ddo1 ce v il and r/w v ih , i out 0 ma, other input v ih /v il t cycle 1 s 15 ma t cycle 70 ns 100 t cycle 85 ns, 100 ns 90 i ddo2 operating current ce 0.2 v and r/w v dd 0.2 v, i out 0 ma, other input v dd 0.2 v/0.2 v t cycle 1 s 10 ma i dds1 ce v ih 3 ma ta 25c 2 5 v dd 2.0 v~5.5 v ta 0~70c 50 ta 25c 2 ta 0~40c 5 a i dds2 standby current ce v dd 0.2 v v dd 3.0 v ta 0~70c 25
tc554161aft-70v,-85v,-10v 2001-08-17 4/11 dc characteristics (ta 0 to 70c, v dd 3 v 10%) symbol parameter test condition min typ max unit i il input leakage current v in 0 v~v dd 1.0 a i lo output leakage current ce v ih or r/w v il or oe v ih , v out 0 v~v dd 1.0 a i oh output high current v oh v dd 0.2 v 0.1 ma i ol output low current v ol 0.2 v 0.1 ma t cycle min 30 i ddo2 operating current ce 0.2 v and r/w v dd 0.2 v, i out 0 ma, other input v dd 0.2 v/0.2 v t cycle 1 s 10 ma ta 25c 2 3 v dd 3.0 v 10% ta 0~70c 28 ta 25c 2 ta 0~40c 5 i dds2 standby current ce v dd 0.2 v v dd 3.0 v ta 0~70c 25 a capacitance (ta 25c, f 1 mhz) symbol parameter test condition max unit c in input capacitance v in gnd 10 pf c out output capacitance v out gnd 10 pf note: this parameter is periodically sampled and is not 100% tested. operating mode mode ce oe r/w lb ub i/o1~i/o8 i/o9~i/o16 power l l output output i ddo h l high-z output i ddo read l l h l h output high-z i ddo l l input input i ddo h l high-z input i ddo write l * l l h input high-z i ddo l h h * * output deselect l * * h h high-z high-z i ddo standby h * * * * high-z high-z i dds * = don't care h = logic high l = logic low
tc554161aft-70v,-85v,-10v 2001-08-17 5/11 ac characteristics and operating conditions (ta 0 to 70c, v dd 5 v 10%) read cycle tc554161aft -70v -85v -10v symbol parameter min max min max min max unit t rc read cycle time 70 85 100 t acc address access time 70 85 100 t co chip enable access time 70 85 100 t oe output enable access time 35 45 50 t ba data byte control access time 35 45 50 t oh output data hold time 10 10 10 t coe chip enable low to output active 10 10 10 t oee output enable low to output active 5 5 5 t be data byte control low to output active 5 5 5 t od chip enable high to output high-z 25 30 35 t odo output enable high to output high-z 25 30 35 t bd data byte control high to output high-z 25 30 35 ns write cycle tc554161aft -70v -85v -10v symbol parameter min max min max min max unit t wc write cycle time 70 85 100 t wp write pulse width 50 55 60 t cw chip enable to end of write 60 70 80 t bw data byte control to end of write 50 55 60 t as address setup time 0 0 0 t wr write recovery time 0 0 0 t ds data setup time 30 35 40 t dh data hold time 0 0 0 t oew r/w high to output active 5 5 5 t odw r/w low to output high-z 25 30 35 ns ac test conditions parameter test condition output load 100 pf 1 ttl gate input pulse level 0.6 v, 2.4 v timing measurements 1.5 v reference level 1.5 v t r , t f 5 ns
tc554161aft-70v,-85v,-10v 2001-08-17 6/11 ac characteristics and operating conditions (ta 0 to 70c, v dd 2.7 v to 5.5 v) read cycle symbol parameter min max unit t rc read cycle time 150 t acc address access time 150 t co chip enable access time 150 t oe output enable access time 75 t ba data byte control access time 75 t oh output data hold time 10 t coe chip enable low to output active 10 t oee output enable low to output active 5 t be data byte control low to output active 5 t od chip enable high to output high-z 50 t odo output enable high to output high-z 50 t bd data byte control high to output high-z 50 ns write cycle symbol parameter min max unit t wc write cycle time 150 t wp write pulse width 100 t cw chip enable to end of write 120 t bw data byte control to end of write 100 t as address setup time 0 t wr write recovery time 0 t ds data setup time 60 t dh data hold time 0 t oew r/w high to output active 5 t odw r/w low to output high-z 50 ns ac test conditions parameter test condition output load 100 pf (include jig) input pulse level v dd 0.2 v, 0.2 v timing measurements 1.5 v reference level 1.5 v t r , t f 5 ns
tc554161aft-70v,-85v,-10v 2001-08-17 7/11 timing diagrans read cycle (see note 1) write cycle 1 (r/w controlled) (see note 4) address r/w ub , lb d out t as t bw t wr valid data in t odw d in t wp t ds t dh t oew (see note 3) (see note 2) hi-z t cw ce t wc (see note 5) (see note 5) address oe d out t rc t acc t od t oh valid data out t oe t be t oee t bd hi-z hi-z t co ce ub , lb t odo t ba t coe indeterminate
tc554161aft-70v,-85v,-10v 2001-08-17 8/11 write cycle 2 ( controlled) (see note 4) write cycle 3 ( , controlled) (see note 4) address t wc t wp r/w ce d out t as t bw t wr valid data in t odw d in t ds t dh t coe hi-z hi-z ub , lb t cw t be (see note 5) (see note 5) t wc address t wp r/w ce d out t as t cw t wr valid data in t odw d in t ds t dh t coe hi-z hi-z ub , lb t bw t be (see note 5) (see note 5) ce ub lb
tc554161aft-70v,-85v,-10v 2001-08-17 9/11 note: (1) r/w remains high for the read cycle. (2) if ce goes low coincident with or after r/w goes low, the outputs will remain at high impedance. (3) if ce goes high coincident with or before r/w goes high, the outputs will remain at high impedance. (4) if oe is high during the write cycle, the outputs will remain at high impedance. (5) because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. data retention characteristics (ta 0 to 70c) symbol parameter min typ max unit v dh data retention supply voltage 2.0 5.5 v v dh 3.0 v 25 * i dds2 standby current v dh 5.5 v 50 a t cdr chip deselect to data retention mode time 0 ns t r recovery time 5 ms * : 5 a (max) at ta 0 to 40c controlled data retention mode note: when ce is operating at the v ih level (2.2v), the standby current is given by i dds1 during the transition of v dd from 4.5 to 2.4v. v dd 4.5 v gnd v ih data retention mode t r (see note) (see note) t cdr v dd 0.2 v ce ce
tc554161aft-70v,-85v,-10v 2001-08-17 10/11 package dimensions weight: 0.57 g (typ)
tc554161aft-70v,-85v,-10v 2001-08-17 11/11 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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